1. Field of the Invention
This invention relates to carriers for electronic components and in particular to carriers for low temperature co-fired ceramic (LTCC) components.
2. Description of the Prior Art
Surface Mount Technology (SMT) is used by the electronics industry as a mass production technique for attaching electronic components to printed circuit boards (PCBs) by reflow soldering. The electronics industry has a continuing need to shrink components in order to decrease the PCB area needed for circuitry, and to fit more circuitry into a given area. One method of shrinking components is to use Low Temperature Co-fired Ceramic, (LTCC) which allows circuitry to be distributed in multiple stacked layers rather than being spread out in a single layer. Examples of LTCC circuitry, are disclosed in U.S. Pat. Nos. 7,049,905, 7,030,713 and 6,784,521. Semiconductor dice can also be attached to to LTCC components in order to further reduce PCB real estate requirements. Typically the semiconductor die is attached to the top layer of the LTCC component and examples of this are disclosed in U.S. Pat. Nos. 7,027,795 and 6,917,796.
Typically, LTCC components use Palladium Silver (PdAg) or gold over nickel for interconnect terminations, and while PdAg has lower cost and greater availability, gold over nickel is superior for less leaching out of metallization during soldering. Historically, gold over nickel has not been available as a finish for most LTCC designs. There exist a significant number of LTCC designs with PdAg finish and one aspect of this invention addresses such designs in terms of providing a finish of gold over nickel instead.
One quality problem in reflow soldering of LTCC components to PCBs is the inspection of solder joints. The typical interconnect termination for an LTCC component is located on the bottom of the component and thus visual inspection of the solder joints is difficult when the component has been soldered in place on a PCB. One technique to allow easier visual inspection of the solder joints involves welding or brazing metal leads to the terminations, though this adds expense and the risk of damage to the terminations. Another technique is to add solderable wraparound metal leads to the LTCC package, which results in reduced real estate for circuitry on the top layer and adds lead inductance, thus reducing high frequency performance.
Another quality problem for LTCC components is in mitigating thermal stress and mechanical shock, which can cause interconnect termination joint failure or even cracking of the component. The coefficient of thermal expansion (CTE) of ceramic and silicon components is sufficiently different from the CTE of typical epoxy fiberglass PCBs that this mismatch can cause solder joint failure with changes in temperature. The CTE mismatch problem is worse for larger components where the amount of thermally induced mechanical stress is greater. Techniques used to provide thermal stress relief for LTCC and semiconductor components generally take the form of an intermediate substrate or interposer, either attached first to the component and thus serving as a carrier, or attached to the PCB, often in the form of a specialized layer. These intermediate structures generally either function by providing a mechanically flexible means to absorb movement and stress generated by CTE mismatch, or by providing an intermediate CTE so that the solder joints on each side of the intermediate structure each see less thermal stress.
U.S. Pat. No. 7,554,206 discloses a flexible substrate with arrays of conductive pads and conductive posts on opposite sides of the substrate and offset from each other to permit movement in response to thermal expansion. This substrate requires numerous manufacturing steps and is a mechanically complex solution to the problem, and since the conductive posts are under the component, provides no improvement to inspection of the resulting solder joints.
U.S. Pat. No. 6,717,819 discloses a flexible substrate having via holes filled with conductive adhesive, where the surfaces of the substrate over the via holes are coated with solderable metal contacts. Since the solderable contacts are under the component it provides no improvement to inspection of the resulting solder joints.
U.S. Pat. No. 6,163,462 discloses a flexible substrate having ball grid arrays on both faces, where the ball grid arrays are connected by conductive vias through the substrate and are either offset or aligned. When offset, the substrate between each pair of solder balls is able to flex and warp in response to thermal stress. When aligned, the substrate has holes interposed between the solder balls to permit more flexure of the substrate. However, in either version the solder joints are under the substrate and thus difficult to inspect.
In U.S. Pat. No. 5,369,551 an interface board is configured to be placed between a leadless component and a PCB. The interface board is made of material having a thermal coefficient similar to that of the PCB. Solder pads on opposite sides of the interface board are offset from each other and PCB material is selectively removed to allow the board to flex. This approach causes the footprint of the PCB to be different than that of the component, which is a major drawback.
In U.S. Pat. No. 5,573,172 a hidden lead package device is placed between a leadless component and a PCB. One end of the hidden lead is brazed to the leadless component and the other end Is soldered to the PCB. This approach causes the footprint of the PCB to be different than that of the component, which is not acceptable in existing PCB designs and in addition, the brazing operation could result in cracking of the LTCC material.
U.S. Pat. No. 4,855,872 discloses a surface mount component attached to an interposer formed from a thin, flexible polymer sheet with conductive traces radiating outward from the component to the sheet edges where the traces can then be soldered to a PCB. The sheet interposer is able to flex in response to thermal stress and the solder joints can be inspected, but requires additional PCB real estate to function and requires the users to design a specialized PCB.
A variant on the flexible substrate approach to mitigating CTE mismatch between surface mount components and PCBs is disclosed in U.S. Pat. No. 4,558,397 wherein a hollow dielectric frame serves as a carrier for the component, using metal clips spanning from the frame's bottom surface to the frame's top surface as conductive elements which the component is soldered to and then in turn the assembly is soldered to the PCB. The disadvantage of this approach is that the metal clips will increase circuit inductance and thus limit high frequency operation, and also have to be manufactured as separate parts and then assembled onto the dielectric frame.
U.S. Pat. No. 4,847,136 discloses a PCB with a relatively thin expansion layer bonded to the surface of the PCB as a means to mitigate CTE mismatch between the PCB and a surface mount component. This approach has the disadvantage of requiring specialized manufacturing for the PCB, requires additional real estate, and also does not address the problem of solder joint inspection since the solder joints are either under the component or are situated at leads extending outwards which lower the usable frequency range of the circuit.
Another approach to mitigating the CTE difference between LTCC components or other ceramic or silicon based components and a PCB substrate is the use of interposers or intermediate mounting substrates with a CTE intermediate that of the component and the PCB. Examples of these intermediate CTE interposers are disclosed in U.S. Pat. Nos. 6,734,540, 6,516,513 and Patent Application 2009/0002963. All three of these inventions provide solder connections under the interposers or substrates and thus provide no improvement in ability to inspect the solder joints.
One form of a carrier for surface mount components is disclosed in U.S. Pat. No. 6,862,190, wherein the carrier adapts the termination footprint of a surface mount device to a different and generally larger footprint on a PCB. This carrier has a generally simple and useful form but has leads long enough to impose limits on high frequency operation and by being substantially larger than the surface mount component is inefficient for mounting the component with a minimal increase in PCB real estate.
There is a need for a cost-effective means to reliably attach an LTCC or other surface mount component to a PCB or similar electronic substrate without leaching of metallization during reflow soldering, with improved capability for visual inspection of the solder joints, with a reduction in thermal stress and mechanical shock on the solder joints, with no significant increase in required PCB real estate required for mounting, and permitting circuit operation at up to and including microwave frequencies.